My Thesis work towards a Master of Science in Computer Engineering from the University of Cincinnati was entitled "Location Cache Design and Performance Analysis for Chip Multiprocessors," and was developed under the advisement of Dr. Wen-Ben Jone. It involved creating a working model of a Location Cache in the Simics full-system simulator, and then analyzing the performance improvements offered by various cache/location cache configurations.
The caches were assumed to use low-power techniques, such as ground gating, currently in use by leading manufacturers such as Intel in order to accurately model power consumption. Power consumption modeling was performed using the CACTI 5.0 cache simulator, which was modified to support both gated-ground caches and location caches.
This 98-page work was published by the University of Cincinnati in their Masters Thesis Registry, and the work was also subsequently adapted as a 14-page work that was published in the January 2011 issue of IEEE Transactions on VLSI Systems.
Masters Thesis - Full text of the Thesis
January 2011 IEEE Transactions on VLSI Systems Article - Shortened and updated version of the work as published by the IEEE
This approximately 10MB zip file contains all of the source documents and code required to recreate this work. It includes the modified implementation of CACTI 5.0, the full Simics cache model, and assorted documentation backing up the various equations and conclusions of the work. If you find it helpful, I'd love to hear about it!