This project involved using VHDL and the Magic layout generator to create a small programmable gate array using the bit-slice design methodology. This was a group project that was a collaboration between Vaishali Vallurupalli and myself. The devices uses a series of lookup tables to accurately represent any logical operation. Our design is limited to two primary inputs 4 bits in size with an additional carry input and carry output so that they could be chained together to form larger arrays. The operation of the device is programmed by serial input to set the lookup tables, which defines the operation of the device.
While its operation is similar to that of a FPGA, this is a much simpler device. FPGAs have a number of design complications that are not addressed by this project.
Before hardware implementation begain, a model of the proposed desgin was created in VHDL down to the structural (gate) level. This allowed us to ensure that our design functioned as intended before proceeding to the time-consuming task of layout design. The behavioral and structural models are included below.
Once the VHDL model was verified to be fully functional, the hardware implementation of the actual chip was performed. This was done using the Magic VLSI CAD tool in Unix. The layout was created by hand without the use of any automatic layout generation tools. The layout, once completed, was then verified using a combonation of the IRSIM switch-level simulator and HSpice.
Once the layout and verification was complete, the design was sent off to the fabrication plant. A few months later, we received the design fully-realized in hardware in a complete packaged format ready for verification. We analysed the functionality of this chip in a later course.
Final Report - Final report on the chip
Updated Progress 1 Report - Updated progress report, included in the final report
Updated Progress 2 Report - Updated progress report, included in the final report
Circuit Schematics - Simple schematic represntation of the design, presented in PDF format (1 MB)
Progress 1 Files - Behavioral VHDL implementation files
Progress 2 Files - Structural VHDL implementation files
Final Project Files - All files related to the final implementation, including magic layout files for the entire design and pin out package. This set is large, at about 11 MB.